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Verilog Adders

ShaunT

The basic adders are simple digital circuits with 1-bit inputs and 1-bit sum and carry.In the following article we are discussing about the Verilog codes for the Half Adder and Full Adder.

The Verilog codes are programmed and simulated using EDA playground and/or Mentor Graphics Model Sim and/or Xilinx Vivado.

Tutorials for how to use HDL programming and Simulation tools.

Basic Half Adder

The half adder consists of two 1-bit inputs, 1-bit sum and carry.

The truth table for half adder is given below:

The diagram below shows the gate level digital logic for simple half adder.

The design and testbench codes for simple half adder is given.

Design

module HA(a_i, b_i, sum_o, carry_o);

    input a_i, b_i;
    output sum_o, carry_o;

    assign sum_o = a_i ^ b_i;
    assign carry_o = a_i & b_i;

endmodule


Testbench

module tb;
   reg a_in, b_in;
   wire sum, carry;
   
   HA dut(a_in, b_in, sum, carry);
   
   initial begin
       a_in=0; b_in=0;
       #10;
       a_in=0; b_in=1;
       #10;
       a_in=1; b_in=0;
       #10;
       a_in=1; b_in=1;
   end
   
endmodule

Basic Full Adder

The full adder consists of three 1-bit inputs, 1-bit sum and carry.

The truth table for full adder is given below:

The diagram below shows the gate level digital logic for simple full adder.

The design and testbench codes for simple full adder is given.

Design

module FA(a_in, b_in, c_in, sum, carry);
   input a_in, b_in, c_in;
   output sum, carry;

   assign sum = a_in ^ b_in ^ c_in;
   assign carry = (a_in & b_in) + (b_in & c_in) + (a_in & c_in);

endmodule

Testbench

module tb;
   reg a_in, b_in, c_in;
   wire sum, carry;

   FA dut(a_in, b_in, c_in, sum, carry);
   
   initial begin
       a_in=0; b_in=0; c_in=0;
       #10;
       a_in=0; b_in=0; c_in=1;
       #10;
       a_in=0; b_in=1; c_in=0;
       #10;
       a_in=0; b_in=1; c_in=1;
       #10;
       a_in=1; b_in=0; c_in=0;
       #10;
       a_in=1; b_in=0; c_in=1;
       #10;
       a_in=1; b_in=1; c_in=0;
       #10;
       a_in=1; b_in=1; c_in=1;
   end
   
endmodule

Full Adder Using Half Adders

Here the half adder module is imported and instantiated to design a full adder. The Verilog code for this design is given below.

Design

module FA(a_in, b_in, c_in, sum, carry);
   input a_in, b_in, c_in;
   output sum, carry;

   wire [2:0] temp;

   HA a1(a_in, b_in,temp[0],temp[1]);
   HA a2(temp[0],c_in,sum,temp[2]);
   assign carry = temp[1] | temp[2];

endmodule



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