Verilog Data Types

Data Values

Verilog supports four types of values for modelling the hardware.

Value	Description
0	Logic high (True Value)
1	Logic low (False Value)
X	Unknown Logic Value (Don’t Care Value)
Z	High Impedance (Floating pin)

NETs

Nets represents the actual connections between the hardware elements or signals. Nets are inferred as actual wires in real hardware implementation. Nets can only be driven using continuous assignment and not in procedural assignment.

Nets are defined using wire keyword in Verilog code.

For example,

• wire a_in; //Declares wire or net of 1-bit length
• wire [7:0] b_in; //Declares wire bus of 8-bits length

If a wire is left uninitialized after declaration, it will take a high impedance value (Z), i.e. it will be in floating state as its default value.

REGISTERs

Register data type represent a storage element. Data is stored in the registers only in the Procedural assignment blocks in Verilog.

Registers are defined using reg keyword in Verilog code.

For example,

• reg a_in; //Declares register of 1-bit size
• reg [7:0] b_in; //Declares register of 8-bits size

Whenever a register is defined, it takes a don’t care value (X), as its default state.

Other Data types in Verilog

Verilog support other data types, namely – integer, real and time data types.

These can be referred to as derived register data types.

Integer:

• Integers in Verilog are declared using the keyword integer.
• The default width of integer depends on the word size of host machine, but it is at least 32-bits.
• Simple registers store only unsigned values, whereas integers store signed values.

Real:

• Real values are declared using the keyword real.
• Floating values can be stored using real data type.
• The default value of real data type is ‘0’.

Time:

• Time data type is declared using the keyword time.
• The width of time data type is at least 64-bits.
• This data type can be used to store the simulation time in Verilog.

We can declare some user-defined constant values using the keyword parameter. These parameters can be overridden while simulation. This can facilitate us to develop a more generalised Verilog code.