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Home > Verilog > Verilog Operators

Verilog Operators

ShaunT

Description

The Verilog codes are programmed and simulated using EDA playground and/or Mentor Graphics Model Sim and/or Xilinx Vivado.

Tutorials for how to use HDL programming and Simulation tools.

Arithmetic Operators

Operator Description
+ Addition: A + B
- Subtraction: A - B
* Multiplication: A * B
/ Division: A / B
** Power(AB): A ** B
% Modulo: A % B

Relational Operators

Operator Description
< Less than: A < B
> Greater than: A > B
<= Less than equal to: A <= B
>= Greater than equal to: A >= B

Equality Operators

Operator Description
== Equal to: A == B
Result can be 0, 1 , X.
!= Not Equal to: A != B
Result can be 0, 1 , X.
=== Equal to: A === B
Result can be 0, 1.
!== Not Equal to: A !== B
Result can be 0, 1.

Logical Operators

Operator Description
&& Logical and: A && B
Result will be 1-bit length.
|| Logical or: A || B
Result will be 1-bit length.
! Logical not: !A
Result will be 1-bit length.

Bit-wise Operators

Operator Description
& A and B: A & B
| A or B: A | B
~ not A: ~A
^ A ex-or B: A ^ B
~^ or ^~ A ex-nor B: A ~^ B

Shift Operators

Operator Description
<< Shift left: A << 1
>> Shift right: A >> 1



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