Verilog Conditional, Case and Looping Statements

Conditional Statements

Conditional Statements are used to execute block of statements depending upon certain conditions.

It is defined using if... else if... else statements. Syntax:

if(condition1) begin
  statement_1;
end
else if(condition2) begin
statement_2;
end
else if(condition3) begin
  statement_3;
end
else begin
  default_statement;
end

Here, condition_1 is considered to have highest priority, followed by condition_2 and default_statement having least priority.

Case Statements

This is similar to the switch case in C language. Syntax:

case(expression)
  case_1 : begin
        statement_1;
      end
  case_2 : begin
        statement_2;
      end
  case_3 : begin
        statement_3;
      end
  default : begin
        default_statement;
      end
endcase

Here, unlike if..else all the cases have same priority.

Looping Statements

• While loop

It is similar to the simple while lop used in C language.

Syntax:
while(condition) begin
  statements;
end

• For loop

It is similar to the simple while lop used in C language.

Syntax and example:
integer i;
for(i=0; i<10; i=i+1) begin
  statements;
end

Note: Verilog does not support incrementation like i++. We should use i=i+1 instead.

• Repeat loop

This loop is used to repeatedly execute a block of code for a fixed number of times as mentioned in the loop.

Syntax:
repeat(number_of_times) begin
  Statements;
end

• Forever loop

This loop is used to infinitely execute a block of code till the end of simulation.

Syntax:
forever begin
  statements;
end