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Home > Verilog > Verilog Modules and Ports

Verilog Modules and Ports

ShaunT

Modules and Ports form are the basic elements of verilog code. Let us discuss both in detail.

Modules

Module is a main design entity in Verilog which implements a certain functionality.

The entire logic for the design coded inside the module block in Verilog.

It is declared using the keyword module. The basic structure of a Verilog program is:


module module_name (port_list);
  port_declaration
  design_logic_statements
endmodule

Ports

Port is the interface between the design and the external environment. For example, the input/output pins of an IC.

All the ports should be mentioned in the port list during module declaration.For example,

  • module adder(a_in, b_in, sum_out);

The ports mentioned in the port list should be declared inside the module. Verilog of ports include three types:

Verilog Keyword Type of Port
input Input port
output Output port
inout Bi-directional port



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