Verilog Encoder and Decoders

Encoder

An encoder is a digital combinational circuit which converts a 2N input lines to N output lines. In case of simple digital encoder, only one input line has active (logic high) at a time.

Truth Table for Encoder:

The Boolean expressions result to:

One drawback of basic encoder is if all inputs are low (i.e. logic ‘0’), the output is ‘000’, which is also the output for condition if D0 is active.

Another drawback of encoder is that only one input can be active at a time. For example, if D7 and D5 are active (i.e. logic ‘1’), the output is ‘111’. Priority encoders are used to overcome this drawback.

Programs:

Design

module encoder(data_in, y_out);
 
	input [7:0] data_in;
	output [2:0] y_out;
	
	assign y_out[2] = data_in[4] | data_in[5] | data_in[6] | data_in[7];
	assign y_out[1] = data_in[2] | data_in[3] | data_in[6] | data_in[7];
	assign y_out[0] = data_in[1] | data_in[3] | data_in[5] | data_in[7];
	
endmodule

Testbench

module tb__encoder;
 
	reg [7:0] data_in;
	wire [2:0] y_out;
 
	integer i;
 
	encoder dut(data_in, y_out);
 
	initial begin
		data_in = 8’b00000001;
		for(i=1; i < 8; i = i + 1) begin
			#10; data_in = data_in << 1;
		end
		$finish;
	end
endmodule

Priority Encoder

The priority encoder is a digital combinational circuit which provides output depending upon the priority of inputs.

When more than one inputs are active (logic ‘1’), the output is generated depending on the highest priority input.

Priority encoder overcomes both the drawbacks mentioned in the encoders. For example, consider the 4 to 2 priority, i.e. 4 input lines and 2 output lines. An extra valid output bit is used. The valid bit is set high whenever any one of the inputs is high and it is set low whenever all input bits are zeros. In this condition the output is not considered.

In this case, D3 input is having the highest priority and D0 input having lowest priority. Here, X denotes don’t care, i.e. it can be either ‘0’ or ‘1’.

Truth Table for Priority Encoder:

Programs:

Design

module priority_encoder(data_in, y_out, valid_out);
 
	input [3:0] data_in;
	output [1:0] y_out;
	output valid_out;
	
	assign valid_out = |data_in;
	assign y_out[0] = ((~data_in[2]) & data_in[1]) | data_in[3];
	assign y_out[1] = data_in[2] | data_in[3];
			
endmodule

Testbench

module tb_priority_encoder;
 
	reg [3:0] data_in;
	wire [1:0] y_out;
	wire valid_out;
 
	integer i;
 
	priority_encoder dut(data_in, y_out, valid_out);
 
	initial begin
		for(i=0; i < 8; i = i + 1) begin
			#10; data_in = $random;
		end
	end
endmodule

Decoder

Decoder is a digital combinational circuit which converts N input lines to 2N output lines. It has function reverse to encoder.

In case of decoder, only one output line is high or active at a time. For example, consider a 3 to 8 decoder.

Truth Table for Decoder:

Programs:

Design

module decoder(data_in, y_out);
	
	input [2:0] data_in;
	output reg [7:0] y_out;
 
	always @ (data_in) begin
		case(in)
			3'b000 : y_out = 8'b0000_0001;
			3'b001 : y_out = 8'b0000_0010;
			3'b010 : y_out = 8'b0000_0100;
			3'b011 : y_out = 8'b0000_1000;
			3'b100 : y_out = 8'b0001_0000;
			3'b101 : y_out = 8'b0010_0000;
			3'b110 : y_out = 8'b0100_0000;
			3'b111 : y_out = 8'b1000_0000;
			default: y_out = 8'b0;
		endcase
	end
endmodule

Testbench

module tb_decoder;
 
	reg [2:0] data_in;
	wire [7:0] y_out;
 
	integer i;
 
	decoder dut(data_in, y_out);
 
	initial begin
		for(i=0; i < 8; i = i + 1) begin
			#10; data_in = $random;
		end
		#10; $finish;
	end
endmodule