Verilog Johnson Counter

Johnson Counter is a sequential circuit where the complemented output of last flip-flop is applied as input to the first stage or flip-flop of the shift register. It is a Synchronous type of counter.

In Johnson Counter, the Number of stages in Counter = 2 * (Number of flip-flops).

Truth Table for Johnson Counter:

The Verilog codes are programmed and simulated using EDA playground and/or Mentor Graphics Model Sim and/or Xilinx Vivado.

Tutorials for how to use HDL programming and Simulation tools.

Programs:

Design

module johnson_counter(clk, rst, q);
 
	parameter WIDTH = 4;
	input clk, rst;
	output reg [WIDTH-1:0] q;
 
	always @ (posedge clk or negedge rst)
	begin
		if(~rst)
			q <= 0; //Initialing to all zeros
		else begin
			q[WIDTH-1:1] <=	q[WIDTH-2:0];
			q[0] <= ~q[WIDTH-1];
		end
	end
endmodule

Testbench

module tb_johnson_counter;
 
	parameter WIDTH = 4;
	reg clk, rst;
	wire [WIDTH-1:0] q;
 
	johnson_counter #(.WIDTH(WIDTH)) //Overriding the parameter defined in design module
       		dut(clk, rst, q);
 
	initial begin
		clk = 0;
		forever begin
			#5; clk = ~clk;
		end
	end
 
	initial begin
		rst = 0;
		#10; rst = 1;
		#100; $finish;
	end
endmodule

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