Verilog Latch and Flip-Flop

D Latch

Program:

Design

module d_latch(rst_n, en, data_in, q_out);

	input rst_n, en, data_in;
	output reg q_out;

	always @ *
	begin
		if(~rst_n) //negative edge triggered reset
			q_out <= 1'b0;
		else if(en)
			q_out <= data_in;
	end
endmodule

Testbench

module tb_d_latch;

	reg rst_n, en, data_in;
	wire q_out;

	integer i;

	d_latch dut(rst_n, en, data_in, q_out);

	initial begin
		rst_n = 0;
		en = 0;
		data_in = 0;

		#10;
		rst_n = 1;
		en = 1;

		for(i = 0; i < 10; i = i + 1) begin
			data_in = $random;
			#10;
		end
	end
endmodule

D Flip-Flop

Program:

Design: Synchronous Reset

module dff(clk, rst_n, data_in, q_out);

	input clk, rst_n, data_in;
	output reg q_out;

	always @ (posedge clk)
	begin
		if(~rst_n) //negative edge triggered reset
			q_out <= 1'b0;
		else
			q_out <= data_in;
	end
endmodule

Design: Asynchronous Reset


module dff(clk, rst_n, data_in, q_out);

	input clk, rst_n, data_in;
	output reg q_out;

	always @ (posedge clk or negedge rst_n)
	begin
		if(~rst_n) //negative edge triggered reset
			q_out <= 1'b0;
		else
			q_out <= data_in;
	end
endmodule

Testbench

module tb_dff;

	reg clk, rst_n, data_in;
	wire q_out;

	integer i;

	dff dut(clk, rst_n, data_in, q_out);

	initial begin
		clk = 0;
		forever begin
			#5; clk = ~clk;
		end
	end

	initial begin
		rst_n = 0;
		data_in = 0;

		#10;
		rst_n = 1;

		for(i = 0; i < 10; i = i + 1) begin
			data_in = $random;
			#8;
		end
		$finish;
	end
endmodule