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Home > Verilog > Multiplexer

Verilog Multiplexer

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Multiplexer(MUX) is a digital logic used to select any one of the multiple inputs and provide it as output. It is a many to one circuit.

The multiplexer has 2n inputs, where n is the number of select lines. The select lines determines which input to be selected. A simple multiplexer can be designed using various ways:

  • Behavioural implementation
  • Using Conditional operator
  • Gate level design

The Verilog codes are programmed and simulated using EDA playground and/or Mentor Graphics Model Sim and/or Xilinx Vivado.

Tutorials for how to use HDL programming and Simulation tools.

2 to 1 Multiplexer

This has two data inputs, one select line and one output. The Verilog codes for 2:1 MUX using various modelling techniques are mentioned below along with the testbench.

The truth table for 2:1 MUX is given below:

The diagram below shows the gate level digital logic for 2:1 MUX.

Programs:

Design: Behavioral

module mux(I0, I1, sel_in, y_out);
	
    input I0, I1, sel_in;
    output reg y_out;
    
    always @ *
    begin
        case(sel_in)
            1'b0 : y_out = I0;
            1'b1 : y_out = I1;
        endcase
    end
 
endmodule


Design: Using Conditional Operator

module mux(I0, I1, sel_in, y_out);
 
    input I0, I1, sel_in;
    output y_out;
    
    assign y_out = sel_in ? I1 : I0;
 
endmodule


Design: Gate Level

module mux(I0, I1, sel_in, y_out);
 
    input I0, I1, sel_in;
    output y_out;
    
    wire [1:0] temp;
    
    and a1(temp[0], ~sel_in, I0);
    and a2(temp[1], sel_in, I1);
    or o1(y_out, temp[0], temp[1]);
    
endmodule


Testbench

module tb_mux;
 
    reg I0, I1, sel_in;
    wire y_out;
    
    mux dut(I0, I1, sel_in, y_out);
    
    initial begin
        I0=0; I1=1; sel_in=0; #10;
        I0=0; I1=1; sel_in=0; #10;
        I0=1; I1=0; sel_in=1; #10;
        I0=1; I1=0; sel_in=1; #10;
    end
 
endmodule

4 to 1 Multiplexer

This has four data inputs, two select line and one output. The Verilog codes for 4:1 MUX using various modelling techniques are mentioned below along with the testbench.

The truth table for 4:1 MUX is given below:

The diagram below shows the gate level digital logic for 4:1 MUX.

The design and testbench codes for simple full adder is given.

Design: Behavioral

module mux(I0, I1, I2, I3, sel0, sel1, y_out);
 
    input I0, I1, I2, I3, sel0, sel1;
    output reg y_out;
    
    always @ *
    begin
        case({sel1,sel0})
            2'b00 : y_out = I0;
            2'b01 : y_out = I1;
            2'b10 : y_out = I2;
            2'b11 : y_out = I3;
        endcase
    end
 
endmodule


Design: Using Conditional Operator

module mux(I0, I1, I2, I3, sel0, sel1, y_out);
 
    input I0, I1, I2, I3, sel0, sel1;
    output y_out;
    
    assign y_out = sel0 ? (sel1 ? I1 : I0) : (sel1 ? I3 : I2);
 
endmodule

4:1 MUX using 2:1 MUX

Here the 2:1 MUX is imported and instantiated three times and interconnected appropriately to form a 4:1 MUX. 

Design

module mux(I0, I1, I2, I3, sel0, sel1, y_out);
 
    input I0, I1, I2, I3, sel0, sel1;
    output y_out;
    
    wire [1:0] temp;
    
    mux_2_1 m1(I0, I1, sel1, temp[0]);
    mux_2_1 m2(I2, I3, sel1, temp[1]);
    mux_2_1 m3(temp[0], temp[1], sel0, y_out);
 
endmodule



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