Verilog Ring Counter

Ring Counter is a circuit that follows the principle of running 1’s. It is similar to shift register, but the only difference is that that output of last flip-flop is provided as an input to first flip-flop.

In ring counter, Number of ring counter states = Number of flip-flops.

As ring counter is an application of shift register, we have a clock provide to all flip-flops. It is a synchronous counter.

Some additional inputs like Clear (CLR) and Preset (PR) can also be applied to the circuit. Generally, these are active low pins.

Truth Table for Ring Counter:

The Verilog codes are programmed and simulated using EDA playground and/or Mentor Graphics Model Sim and/or Xilinx Vivado.

Tutorials for how to use HDL programming and Simulation tools.

Programs:

Design

module ring_counter(clk, clr, pr, q);
 
	parameter WIDTH = 4;
	input clk, clr, pr;
	output reg [WIDTH-1:0] q;
 
	always @ (posedge clk or negedge clr)
	begin
		if(!clr)
			q <= 0; //Initialing to all zeros
		else if(!pr) begin
			q <= 1; //Preset to 1
		end
		else begin
			q[WIDTH-1:1] <=	q[WIDTH-2:0];
			q[0] <= q[WIDTH-1];
		end
	end
endmodule

Testbench

module tb_ring_counter;
 
	parameter WIDTH = 5;
	reg clk, clr, pr;
	wire [WIDTH-1:0] q;

	ring_counter #(.WIDTH(WIDTH)) //Overriding the parameter defined in design module
       		dut(clk, clr, pr, q);
 
	initial begin
		clk = 0;
		forever begin
			#5; clk = ~clk;
		end
	end
 
	initial begin
		clr = 0;
		pr = 0;
 
		#10; clr = 1;
		#10; pr = 1;
		#100; $finish;
	end
endmodule

---