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Verilog Sequence Detector

ShaunT

Description

The Verilog codes are programmed and simulated using EDA playground and/or Mentor Graphics Model Sim and/or Xilinx Vivado.

Tutorials for how to use HDL programming and Simulation tools.

Mealy FSM without sequence overlap

Program:

Design

module seq_detect(
   input d_in, clk, reset_n, 
   output reg q_out);

	parameter s0=3'b000;
	parameter s1=3'b001;
	parameter s2=3'b010;
	parameter s3=3'b011;
	parameter s4=3'b100;
	parameter s5=3'b101;
	
	reg [2:0] current_state, next_state;

	always @ (posedge clk or posedge reset_n)
	begin : state_register
		if(reset_n)
			current_state <= s0;
		else
			current_state <= next_state;	
	end
	always @ (*)
	begin : next_state_logic	
		case(current_state)
            s0 : 
                if(d_in)
                    next_state = s1;
                else
                    next_state = s0;
            s1 : 
                if(d_in)
                    next_state = s1;
                else
                    next_state = s2;
            s2 : 
                if(d_in)
                    next_state = s3;
                else
                    next_state = s0;
            s3 : 
                if(d_in)
                    next_state = s1;
                else
                    next_state = s4;
            s4 : 
                if(d_in)
                    next_state = s1;
                else
                    next_state = s5;
            s5 : 
                if(d_in)
                    next_state = s0;
                else
                    next_state = s0;
            default : if(d_in)
                        next_state = s0;
                    else
                        next_state = s0;
		endcase
	end
	always @ (current_state,d_in)
	begin : output_logic
		case(current_state)
            s0 : q_out = 1'b0;
            s1 : q_out = 1'b0;
            s2 : q_out = 1'b0;
            s3 : q_out = 1'b0;
            s4 : q_out = 1'b0;
            s5 : if(d_in)
                        q_out = 1'b1;
                    else
                        q_out = 1'b0;		
		   default : q_out = 1'b0;
		endcase
	end
endmodule

Testbench

module tb_seq_detect;

    // Inputs
	reg d_in;
	reg clk;
	reg reset_n;

	// Outputs
	wire q_out;
	
	integer i;
	reg [20:0] test_data;

	seq_detect dut (
		.d_in(d_in), 
		.clk(clk), 
		.reset_n(reset_n), 
		.q_out(q_out)
	);

	initial begin
	   clk = 0;
	   forever begin
	       #5; clk = ~clk;
	   end
	end
	initial begin
		 reset_n = 1;
		 test_data = 21'b0101_0010_1001_0001_0100_1;
		 
		 #20; reset_n = 0;
		 for(i = 20; i >= 0; i = i - 1) begin
		      @(negedge clk);
		      d_in = test_data[i];
		 end
		 #20; $finish;
	end
endmodule

Mealy FSM with sequence overlap

Program:

Design

module seq_detect(
  	input d_in, clk, reset_n, 
   output reg q_out);

	parameter s0=3'b000;
	parameter s1=3'b001;
	parameter s2=3'b010;
	parameter s3=3'b011;
	parameter s4=3'b100;
	parameter s5=3'b101;
	
	reg [2:0] current_state, next_state;

	always @ (posedge clk or posedge reset_n)
	begin : state_register
		if(reset_n)
			current_state <= s0;
		else
			current_state <= next_state;	
	end
	always @ (*)
	begin : next_state_logic	
		case(current_state)
            s0 : if(d_in)
                    next_state = s1;
                else
                    next_state = s0;
                        
            s1 : if(d_in)
                    next_state = s1;
                else
                    next_state = s2;
                        
            s2 : if(d_in)
                    next_state = s3;
                else
                    next_state = s0;
                        
            s3 : if(d_in)
                    next_state = s1;
                else
                    next_state = s4;
                        
            s4 : if(d_in)
                    next_state = s1;
                else
                    next_state = s5;
                        
            s5 : if(d_in)
                    next_state = s1;
                else
                    next_state = s0;
            default : if(d_in)
                        next_state = s0;
                    else
                        next_state = s0;
		endcase
	end
	always @ (current_state,d_in)
	begin : output_logic
		case(current_state)
            s0 : q_out = 1'b0;
            s1 : q_out = 1'b0;
            s2 : q_out = 1'b0;
            s3 : q_out = 1'b0;
            s4 : q_out = 1'b0;
            s5 : if(d_in)
                        q_out = 1'b1;
                    else
                        q_out = 1'b0;		
		   default : q_out = 1'b0;
		endcase
	end
endmodule

Testbench

module tb_seq_detect;

   // Inputs
	reg d_in;
	reg clk;
	reg reset_n;

	// Outputs
	wire q_out;
	
	integer i;
	reg [20:0] test_data;

	seq_detect dut (
		.d_in(d_in), 
		.clk(clk), 
		.reset_n(reset_n), 
		.q_out(q_out)
	);

	initial begin
	   clk = 0;
	   forever begin
	       #5; clk = ~clk;
	   end
	end
	initial begin
		 reset_n = 1;
		 test_data = 21'b0101_0010_1001_0001_0100_1;
		 
		 #20; reset_n = 0;
		 for(i = 20; i >= 0; i = i - 1) begin
		      @(negedge clk);
		      d_in = test_data[i];
		 end
		 #20; $finish;
	end
endmodule

Moore FSM without sequence overlap

Program:

Design

module seq_detect(
    input d_in, clk, reset_n, 
    output reg q_out);

	parameter s0=3'b000;
	parameter s1=3'b001;
	parameter s2=3'b010;
	parameter s3=3'b011;
	parameter s4=3'b100;
	parameter s5=3'b101;
	parameter s6=3'b110;
	
	reg [2:0] current_state, next_state;

	always @ (posedge clk or posedge reset_n)
	begin : state_register
		if(reset_n)
			current_state <= s0;
		else
			current_state <= next_state;		
	end
	always @ (*)
	begin : next_state_logic	
		case(current_state)
            s0 : if(d_in)
                    next_state = s1;
                else
                    next_state = s0;
                        
            s1 : if(d_in)
                    next_state = s1;
                else
                    next_state = s2;
                        
            s2 : if(d_in)
                    next_state = s3;
                else
                    next_state = s0;
                        
            s3 : if(d_in)
                    next_state = s1;
                else
                    next_state = s4;
                        
            s4 : if(d_in)
                    next_state = s1;
                else
                    next_state = s5;
                        
            s5 : if(d_in)
                    next_state = s6;
                else
                    next_state = s0;
                        
            s6 : if(d_in)
                    next_state = s1;
                else
                    next_state = s0;
                        
            default : if(d_in)
                        next_state = s0;
                    else
                        next_state = s0;
		endcase
	end
	always @ (current_state)
	begin : output_logic
		case(current_state)
            s0 : q_out = 1'b0;
            s1 : q_out = 1'b0;
            s2 : q_out = 1'b0;
            s3 : q_out = 1'b0;
            s4 : q_out = 1'b0;
            s5 : q_out = 1'b0;
            s6 : q_out = 1'b1;			
		   default : q_out = 1'b0;
		endcase
	end
endmodule

Testbench

module tb_seq_detect;

    // Inputs
	reg d_in;
	reg clk;
	reg reset_n;

	// Outputs
	wire q_out;
	
	integer i;
	reg [20:0] test_data;

	seq_detect dut (
		.d_in(d_in), 
		.clk(clk), 
		.reset_n(reset_n), 
		.q_out(q_out)
	);

	initial begin
	   clk = 0;
	   forever begin
	       #5; clk = ~clk;
	   end
	end
	initial begin
		 reset_n = 1;
		 test_data = 21'b0101_0010_1001_0001_0100_1;
		 #20; reset_n = 0;
		 for(i = 20; i >= 0; i = i - 1) begin
		      @(negedge clk);
		      d_in = test_data[i];
		 end
		 #20;
		 $finish; 
	end      
endmodule

Moore FSM with sequence overlap

Program:

Design

module seq_detect(
   input d_in, clk, reset_n, 
   output reg q_out);

	parameter s0=3'b000;
	parameter s1=3'b001;
	parameter s2=3'b010;
	parameter s3=3'b011;
	parameter s4=3'b100;
	parameter s5=3'b101;
	parameter s6=3'b110;
	
	reg [2:0] current_state, next_state;

	always @ (posedge clk or posedge reset_n)
	begin : state_register
		if(reset_n)
			current_state <= s0;
		else
			current_state <= next_state;	
	end
	always @ (*)
	begin : next_state_logic	
		case(current_state)
            s0 : if(d_in)
                    next_state = s1;
                else
                    next_state = s0;
            s1 : if(d_in)
                    next_state = s1;
                else
                    next_state = s2;
            s2 : if(d_in)
                    next_state = s3;
                else
                    next_state = s0;
            s3 : if(d_in)
                    next_state = s1;
                else
                    next_state = s4;
            s4 : if(d_in)
                    next_state = s1;
                else
                    next_state = s5;
            s5 : if(d_in)
                    next_state = s6;
                else
                    next_state = s0;
            s6 : if(d_in)
                    next_state = s1;
                else
                    next_state = s2;                  
            default : if(d_in)
                        next_state = s0;
                    else
                        next_state = s0;
		endcase
	end
	always @ (current_state)
	begin : output_logic	
		case(current_state)
            s0 : q_out = 1'b0;
            s1 : q_out = 1'b0;
            s2 : q_out = 1'b0;
            s3 : q_out = 1'b0;
            s4 : q_out = 1'b0;
            s5 : q_out = 1'b0;
            s6 : q_out = 1'b1;
		   default : q_out = 1'b0;
		endcase
	end
endmodule

Testbench

module tb_seq_detect;

   // Inputs
	reg d_in;
	reg clk;
	reg reset_n;

	// Outputs
	wire q_out;
	
	integer i;
	reg [20:0] test_data;

	seq_detect dut (
		.d_in(d_in), 
		.clk(clk), 
		.reset_n(reset_n), 
		.q_out(q_out)
	);

	initial begin
	   clk = 0;
	   forever begin
	       #5; clk = ~clk;
	   end
	end
	initial begin
		 reset_n = 1;
		 test_data = 21'b0101_0010_1001_0001_0100_1;
		 #20; reset_n = 0;
		 for(i = 20; i >= 0; i = i - 1) begin
		      @(negedge clk);
		      d_in = test_data[i];
		 end
		 #20; $finish;
	end
endmodule

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