Verilog Up/Down Counter

A counter is digital sequential circuit that counts from zero to a predefined count. In up/down counter, we have an option to choose whether to count in ascending or descending order.

If a counter is of N-bits, we can count upto 2^N -1.

In up/down counter, clock, reset inputs. We also have an input named upDown to select whether to up count or down count. If upDown = 1, do up counting and if upDown = 0, perform down counting.

For additional functionality, we can add a data input, to load an initial state of the counter.

The Verilog codes are programmed and simulated using EDA playground and/or Mentor Graphics Model Sim and/or Xilinx Vivado.

Tutorials for how to use HDL programming and Simulation tools.

Programs:

Design

module up_down_counter(clk, rst, upDown, data_in, load, q_out);
 
	parameter WIDTH = 4;
	input clk, rst, upDown, load;
	input [WIDTH-1:0] data_in;
	output [WIDTH-1:0] q_out;
	reg [WIDTH-1:0] temp;
 
	always @ (posedge clk or posedge rst)
	begin
		if(rst)
			temp <= 0; //Reset
		else if(load)
			temp <= data_in; //Load Data
		else if(upDown)
			temp <= temp + 1; //Up Counter
		else
			temp <= temp - 1;  //Down Counter
	end
	assign q_out = temp;	
endmodule

Testbench

module tb_up_down_counter;

	parameter WIDTH = 4;
	reg clk, rst, upDown, load;
	reg [WIDTH-1:0] data_in;
	wire [WIDTH-1:0] q_out;

	up_down_counter #(.WIDTH(WIDTH)) //Overriding WIDTH in design module
			dut (clk, rst, upDown, data_in, load, q_out);

	initial begin
		clk = 0;
		forever begin
			#5; clk = ~clk;
		end
	end

	initial begin
		rst = 1;
		load = 0;
		upDown = 1;
		data_in = 0;

		#10;
		rst = 0;
		load = 1;
		data_in = 3;

		#10; load = 0;
		#100; upDown = 0;
		#100; $finish;
	end
endmodule

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